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1 of 33 april 23, 2008 ? 2008 integrated device technology, inc. dsc 6923 ? idt and the idt logo are regi stered trademarks of integrated device technology, inc. device overview the 89hpes24t6 is a member of t he idt precise? family of pci express? switching solutions. t he pes24t6 is a 24-lane, 6-port periph- eral chip that performs pci express packet switching with a feature set optimized for high performance applicat ions such as servers, storage, and communications/networking. it pr ovides connectivity and switching functions between a pci express upstream port and up to five down- stream ports and supports swit ching between downstream ports. features ? high performance pci express switch ? twenty-four 2.5 gbps pci express lanes ? six switch ports ? upstream port configurable up to x8 ? downstream ports configurable up to x8 ? low-latency cut-through switch architecture ? support for max payload size up to 2048 bytes ? one virtual channel ? eight traffic classes ? pci express base specification revision 1.1 compliant ? flexible architecture with nume rous configuration options ? automatic per port link width negotiation to x8, x4, x2 or x1 ? automatic lane reversal on all ports ? automatic polarity inversion on all lanes ? ability to load device conf iguration from serial eeprom ? legacy support ? pci compatible intx emulation ? bus locking ? highly integrated solution ? requires no external components ? incorporates on-chip internal memory for packet buffering and queueing ? integrates twenty-four 2.5 gbps embedded serdes with 8b/ 10b encoder/decoder (no separate transceivers needed) ? reliability, availability, and serviceability (ras) features ? supports ecrc and advanced error reporting ? internal end-to-end parity protecti on on all tlps ensures data integrity even in systems t hat do not implement end-to-end crc (ecrc) ? supports pci express native hot-plug, hot-swap capable i/o ? compatible with hot-plug i/o expanders used on pc and server motherboards block diagram figure 1 internal block diagram 6-port switch core / 24 pci express lanes frame buffer route table port arbitration scheduler serdes phy logical layer serdes phy logical layer serdes phy logical layer multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer serdes phy logical layer serdes phy logical layer serdes phy logical layer multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer serdes phy logical layer serdes phy logical layer serdes phy logical layer multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer (port 0) (port 1) (port 5) 89hpes24t6 data sheet 24-lane 6-port pci express? switch
2 of 33 april 23, 2008 idt 89hpes24t6 data sheet ? power management ? utilizes advanced low-power desi gn techniques to achieve low typical power consumption ? supports pci power management interface specification (pci-pm 1.1) ? supports device power management states: d0, d3 hot and d3 cold ? unused serdes are disabled ? testability and debug features ? ability to read and write any in ternal register via the smbus ? eleven general purpo se input/output pins ? each pin may be individually co nfigured as an input or output ? each pin may be individually co nfigured as an interrupt input ? some pins have selectable alternate functions ? packaged in 27x27mm 420-ball bga with 1mm ball spacing product description utilizing standard pci express in terconnect, the pes24t6 provides the most efficient i/o connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. it provides c onnectivity for up to 6 ports across 24 integrated serial lanes. each lane provides 2.5 gbps of bandwidth in both directions and is fully compliant with pci express base specifica- tion revision 1.1. smbus interface the pes24t6 contains two smbus interfaces. the slave interface provides full access to the conf iguration registers in the pes24t6, allowing every configuration register in the device to be read or written by an external agent. the master inte rface allows the default configura- tion register values of the pes24t 6 to be overridden following a reset with values programmed in an exte rnal serial eeprom. the master interface is also used by an external hot-plug i/o expander. six pins make up each of the tw o smbus interfaces. these pins consist of an smbus clock pin, an smbus data pin, and 4 smbus address pins. in the slave interfac e, these address pins allow the smbus address to which the device responds to be configured. in the master interface, these address pi ns allow the smbus address of the serial configuration eeprom from which data is loaded to be config- ured. the smbus address is set up on negation of perstn by sampling the corresponding address pi ns. when the pins are sampled, the resulting address is as signed as shown in table 1. as shown in figure 2, the master and slave smbuses may be used in a unified or split configuration. in the unified configuration, shown in figure 2(a), the master and slave smbuses are tied together and the pes24t6 acts both as a smbus master as well as a smbus slave on this bus. this requires that the smbus master or processor that has access to pes24t6 registers suppor ts smbus arbitration. in some systems, this smbus master in terface may be implemented using general purpose i/o pins on a proces sor or micro controller, and may not support smbus arbitration. to support these systems, the pes24t6 may be configured to operate in a spli t configuration as shown in figure 2(b). in the split configuration, the master and slave smbuses operate as two independent buses and thus multi- master arbitration is never required. the pes24t6 supports r eading and writing of the serial eeprom on the master smbus via the slave smbus, allowing in system programming of the serial eeprom. bit slave smbus address master smbus address 1 ssmbaddr[1] msmbaddr[1] 2 ssmbaddr[2] msmbaddr[2] 3 ssmbaddr[3] msmbaddr[3] 4 0 msmbaddr[4] 5 ssmbaddr[5] 1 61 0 71 1 table 1 master and slave smbus address assignment
3 of 33 april 23, 2008 idt 89hpes24t6 data sheet figure 2 smbus interface configuration examples hot-plug interface the pes24t6 supports pci express hot-plug on each downstream port. to reduce the number of pins required on the device, the pes 24t6 utilizes an external i/o expander, such as that used on pc mother boards, connected to the smbus mast er interface. following res et and configura- tion, whenever the state of a hot-plug out put needs to be modified, the pes24t6 generat es an smbus transaction to the i/o expan der with the new value of all of the outputs. whenever a hot-plug input changes , the i/o expander generates an interrupt which is received on th e ioexpintn input pin (alternate function of gpio) of the pes24t6. in response to an i/o expander interrupt, the pes24t6 generates an smbus transacti on to read the state of all of the hot-plug inputs from the i/o expander. general purpose input/output the pes24t6 provides 11 general purpose input/output (gpio) pins that may be used by the system designer as bit i/o ports. each gpio pin may be configured independently as an input or output through software control. some gpio pins are shared with other on-chip fu nctions. these alternate functions may be enabled via software, smbus slave interface, or seri al configuration eeprom. the pes24t6 is based on a flexible and effici ent layered architecture. the pci express layer consists of serdes, physical, data link and trans- action layers in compliance with pci expr ess base specification revision 1.1. the pes24t6 can operate either as a store and for ward or cut-through switch and is designed to switch memory and i/o transactions. it supports eight traf fic classes (tcs) and one virtual channel ( vc) with sophisticated resource management to enable efficient switching and i/o connectivity for servers, st orage, and embedded applications. figure 3 i/o expansion application processor pes24t6 ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom processor pes24t6 ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom ... ... (a) unified configuration and management bus (b) split configurati on and management buses memory memory memory processor memory north bridge pes24t6 pes24t6 pes24t6 i/o 10gbe i/o 10gbe i/o sata i/o sata pci express slots
4 of 33 april 23, 2008 idt 89hpes24t6 data sheet pin description the following tables list the functions of the pins provided on the pes24t6. some of the functions listed may be multiplexed on to the same pin. the active polarity of a signal is defined using a suffix. signals ending with an ?n? are defi ned as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses, and select lines) will be interpret ed as being active, or asserted, when at a logic one (high) level. signal type name/description pe0rp[3:0] pe0rn[3:0] i pci express port 0 serial data receive. differential pci express receive pairs for port 0. port 0 is the upstream port. pe0tp[3:0] pe0tn[3:0] o pci express port 0 serial data transmit. differential pci express trans- mit pairs for port 0. port 0 is the upstream port. pe1rp[3:0] pe1rn[3:0] i pci express port 1 serial data receive. differential pci express receive pairs for port 1. when port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. pe1tp[3:0] pe1tn[3:0] o pci express port 1 serial data transmit. differential pci express trans- mit pairs for port 1. when port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. pe2rp[3:0] pe2rn[3:0] i pci express port 2 serial data receive. differential pci express receive pairs for port 2. pe2tp[3:0] pe2tn[3:0] o pci express port 2 serial data transmit. differential pci express trans- mit pairs for port 2. pe3rp[3:0] pe3rn[3:0] i pci express port 3 serial data receive. differential pci express receive pairs for port 3. when port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. pe3tp[3:0] pe3tn[3:0] o pci express port 3 serial data transmit. differential pci express trans- mit pairs for port 3. when port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. pe4rp[3:0] pe4rn[3:0] i pci express port 4 serial data receive. differential pci express receive pairs for port 4. pe4tp[3:0] pe4tn[3:0] o pci express port 4 serial data transmit. differential pci express trans- mit pairs for port 4. pe5rp[3:0] pe5rn[3:0] i pci express port 5 serial data receive. differential pci express receive pairs for port 5. when port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. pe5tp[3:0] pe5tn[3:0] o pci express port 5 serial data transmit. differential pci express trans- mit pairs for port 5. when port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. perefclkp[2:1] perefclkn[2:1] i pci express reference clock. differential reference clock pair input. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic and on-chip serdes. the frequency of the dif- ferential reference clock is determined by the refclkm signal. refclkm i pci express reference clock mode select. this signal selects the fre- quency of the reference clock input. 0x0 - 100 mhz 0x1 - 125 mhz table 2 pci express interface pins
5 of 33 april 23, 2008 idt 89hpes24t6 data sheet signal type name/description msmbaddr[4:1] i master smbus address. these pins determine the smbus address of the serial eeprom from which configuration information is loaded. msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus. it is active and generating the clock only when the eeprom or i/o expand ers are being accessed. msmbdat i/o master smbus data. this bidirectional signal is used for data on the mas- ter smbus. ssmbaddr[5,3:1] i slave smbus address. these pins determine the smbus address to which the slave smbus interface responds. ssmbclk i/o slave smbus clock. this bidirectional signal is used to synchronize trans- fers on the slave smbus. ssmbdat i/o slave smbus data. this bidirectional signal is used for data on the slave smbus. table 3 smbus interface pins signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p2rstn alternate function pin type: output alternate function: reset output for downstream port 2 gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p4rstn alternate function pin type: output alternate function: reset output for downstream port 4 gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn0 alternate function pin type: input alternate function: i/o expander interrupt 0 input gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn1 alternate function pin type: input alternate function: i/o expander interrupt 1 input gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn2 alternate function pin type: input alternate function: i/o expander interrupt 2 input gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn3 alternate function pin type: input alternate function: i/o expander interrupt 3 input table 4 general purpose i/o pins (part 1 of 2)
6 of 33 april 23, 2008 idt 89hpes24t6 data sheet gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: gpen alternate function pin type: output alternate function: general purpose event (gpe) output gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p1rstn alternate function pin type: output alternate function: reset output for downstream port 1 gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p3rstn alternate function pin type: output alternate function: reset output for downstream port 3 gpio[10] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p5rstn alternate function pin type: output alternate function: reset output for downstream port 5 signal type name/description cclkds i common clock downstream. when the cclkds pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. cclkus i common clock upstream. when the cclkus pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port. msmbsmode i master smbus slow mode. the assertion of this pin indicates that the master smbus should operate at 100 khz instead of 400 khz. this value may not be overridden. p01mergen i port 0 and 1 merge. p01mergen is an active low signal. it is pulled low internally via a 251k ohm resistor. when this pin is low, port 0 is merged with port 1 to form a single x8 port. the serdes lanes associated with port 1 become lanes 4 through 7 of port 0. when this pin is high, port 0 and port 1 are not merged, and each oper- ates as a single x4 port p23mergen i port 2 and 3 merge. p23mergen is an active low signal. it is pulled low internally via a 251k ohm resistor. when this pin is low, port 2 is merged with port 3 to form a single x8 port. the serdes lanes associated with port 3 become lanes 4 through 7 of port 2. when this pin is high, port 2 and port 3 are not merged, and each oper- ates as a single x4 port. table 5 system pins (part 1 of 2) signal type name/description table 4 general purpose i/o pins (part 2 of 2)
7 of 33 april 23, 2008 idt 89hpes24t6 data sheet p45mergen i port 4 and 5 merge. p45mergen is an active low signal. it is pulled low internally via a 251k ohm resistor. when this pin is low, port 4 is merged with port 5 to form a single x8 port. the serdes lanes associated with port 5 become lanes 4 through 7 of port 4. when this pin is high, port 4 and port 5 are not merged, and each oper- ates as a single x4 port. perstn i fundamental reset. assertion of this signal resets all logic inside the pes24t6 and initiates a pci express fundamental reset. rsthalt i reset halt. when this signal is asserted during a pci express fundamental reset, the pes24t6 executes the reset procedure and remains in a reset state with the master and slave smbuses active. this allows software to read and write registers internal to the device before normal device opera- tion begins. the device exits the reset state when the rsthalt bit is cleared in the swctl register by an smbus master. swmode[3:0] i switch mode. these configuration pins determine the pes24t6 switch operating mode. these pins should be static and not change after the negation of perstn. 0x0 - normal switch mode 0x1 - normal switch mode with serial eeprom initialization 0x2 - through 0xf reserved signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board table 6 test pins signal type name/description table 5 system pins (part 2 of 2)
8 of 33 april 23, 2008 idt 89hpes24t6 data sheet signal type name/description v dd core i core v dd . power supply for core logic. v dd io i i/o v dd . lvttl i/o buffer power supply. v dd pe i pci express digital power. pci express digital power used by the digital power of the serdes. v dd ape i pci express analog power. pci express analog power used by the pll and bias generator. v tt pe i pci express termination power. v ss i ground. table 7 power and ground pins
9 of 33 april 23, 2008 idt 89hpes24t6 data sheet pin characteristics note: some input pads of the pes24t6 do not contain internal pull- ups or pull-downs. unused inputs should be tied off to appropriate levels. this is especially crit ical for unused control signal inputs which, if le ft floating, could adverse ly affect operation. also, any input pin left floating can cause a slight in crease in power consumption. function pin name type buffer i/o type internal resistor 1 notes pci express inter- face pe0rn[3:0] i cml serial link pe0rp[3:0] i pe0tn[3:0] o pe0tp[3:0] o pe1rn[3:0] i pe1rp[3:0] i pe1tn[3:0] o pe1tp[3:0] o pe2rn[3:0] i pe2rp[3:0] i pe2tn[3:0] o pe2tp[3:0] o pe3rn[3:0] i pe3rp[3:0] i pe3tn[3:0] o pe3tp[3:0] o pe4rn[3:0] i pe4rp[3:0] i pe4tn[3:0] o pe4tp[3:0] o pe5rn[3:0] i pe5rp[3:0] i pe5tn[3:0] o pe5tp[3:0] o perefclkn[2:1] i lvpecl/ cml diff. clock input refer to table 9 perefclkp[2:1] i refclkm i lvttl input pull-down smbus msmbaddr[4:1] i lvttl input pull-up msmbclk i/o sti 2 pull-up on board msmbdat i/o sti pull-up on board ssmbaddr[5,3:1] i input pull-up ssmbclk i/o sti pull-up on board ssmbdat i/o sti pull-up on board general purpose i/o gpio[10:0] i/o lvttl high drive pull-up table 8 pin characteristics (part 1 of 2)
10 of 33 april 23, 2008 idt 89hpes24t6 data sheet system pins cclkds i lvttl input pull-up cclkus i pull-up msmbsmode i pull-down perstn i p01mergen i pull-down p23mergen i pull-down p45mergen i pull-down rsthalt i pull-down swmode[3:0] i pull-down ejtag / jtag jtag_tck i lvttl sti pull-up jtag_tdi i sti pull-up jtag_tdo o jtag_tms i sti pull-up jtag_trst_n i sti pull-up external pull-down 1. internal resistor values under ty pical operating conditions are 54k for pull-up and 251k for pull-down. 2. schmitt trigger input (sti). function pin name type buffer i/o type internal resistor 1 notes table 8 pin characteristics (part 2 of 2)
11 of 33 april 23, 2008 idt 89hpes24t6 data sheet logic diagram ? pes24t6 figure 4 pes24t6 logic diagram reference clocks perefclkp perefclkn jtag_tck gpio[10:0] 11 general purpose i/o v dd core v dd io v dd pe v dd pe power/ground msmbaddr[4:1] msmbclk msmbdat 4 ssmbaddr[5,3:1] ssmbclk ssmbdat 4 master smbus interface slave smbus interface cclkus rsthalt system functions jtag_tdi jtag_tdo jtag_tms jtag_trst_n jtag v ss swmode[3:0] 4 2 2 cclkds perstn refclkm msmbsmode v tt pe pe0rp[0] pe0rn[0] pe0rp[3] pe0rn[3] pci express switch serdes input pe0tp[0] pe0tn[0] pe0tp[3] pe0tn[3] pci express switch serdes output ... port 0 port 0 ... pe1rp[0] pe1rn[0] pe1rp[3] pe1rn[3] pci express switch serdes input pe1tp[0] pe1tn[0] pe1tp[3] pe1tn[3] pci express switch serdes output ... port 1 port 1 ... pe2rp[0] pe2rn[0] pe2rp[3] pe2rn[3] pci express switch serdes input pe2tp[0] pe2tn[0] pe2tp[3] pe2tn[3] pci express switch serdes output ... port 2 port 2 ... pe3rp[0] pe3rn[0] pe3rp[3] pe3rn[3] pci express switch serdes input pe3tp[0] pe3tn[0] pe3tp[3] pe3tn[3] pci express switch serdes output ... port 3 port 3 ... pe4rp[0] pe4rn[0] pe4rp[3] pe4rn[3] pci express switch serdes input pe4tp[0] pe4tn[0] pe4tp[3] pe4tn[3] pci express switch serdes output ... port 4 port 4 ... pe5tp[0] pe5tn[0] pe5tp[3] pe5tn[3] pci express switch serdes output port 5 ... pe5rp[0] pe5rn[0] pe5rp[3] pe5rn[3] pci express switch serdes input ... port 5 pes24t6 p23mergen p01mergen p45mergen
12 of 33 april 23, 2008 idt 89hpes24t6 data sheet system clock parameters values based on systems running at recommended supply voltage s and operating temperatures, as shown in tables 13 and 14. ac timing characteristics parameter description min typical max unit refclk freq input reference clock frequency range 100 125 1 1. the input clock frequency will be either 100 or 125 mhz depending on signal refclkm. mhz refclk dc 2 2. clkin must be ac coupled. use 0.01 ? 0.1 f ceramic capacitors. duty cycle of input clock 40 50 60 % t r , t f rise/fall time of input clocks 0.2*rcui rcui 3 3. rcui (reference clock unit interval) re fers to the reference clock period. v sw differential input voltage swing 4 4. ac coupling required. 0.6 1.6 v t jitter input clock jitter (cycle-to-cycle) 125 ps r t termination resistor 110 ohms table 9 input clock requirements parameter description min 1 typical 1 max 1 units pcie transmit ui unit interval 399.88 400 400.12 ps t tx-eye minimum tx eye width 0.7 .9 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.15 ui t tx-rise , t tx-fall d+ / d- tx output rise/fall time 50 90 ps t tx- idle-min minimum time in idle 50 ui t tx-idle-set-to- idle maximum time to transition to a valid idle after sending an idle ordered set 20 ui t tx-idle-to-diff- data maximum time to transition from valid idle to diff data 20 ui t tx-skew transmitter data skew between any 2 lanes 500 1300 ps pcie receive ui unit interval 399.88 400 400.12 ps t rx-eye (with jitter) minimum receiver eye width (jitter tolerance) 0.4 ui table 10 pcie ac timing characteristics (part 1 of 2)
13 of 33 april 23, 2008 idt 89hpes24t6 data sheet t rx-eye-medium to max jitter max time between jitter median & max deviation 0.3 ui t rx-idle-det-diff- enter time unexpected idle enter detect threshold integration time 10 ms t rx-skew lane to lane input skew 20 ns 1. minimum, typical, and maximum values meet the requirements under pci specification 1.1 signal symbol reference edge min max unit timing diagram reference gpio gpio[10:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw 2 2. the values for this symbol were determined by calculation, not by testing. none 50 ? ns table 11 gpio ac timing characteristics signal symbol reference edge min max unit timing diagram reference jtag jtag_tck tper_16a none 50.0 ? ns see figure 5. thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, reco mmends that jtag_tms should be held at 1 while the signal applied at jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag _tck when jtag_tms is low, because the tap controller might go to eith er the run-test/idle state or stay in the test-logic-reset sta te. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 20 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ?20ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 12 jtag ac timing characteristics parameter description min 1 typical 1 max 1 units table 10 pcie ac timing characteristics (part 2 of 2)
14 of 33 april 23, 2008 idt 89hpes24t6 data sheet figure 5 jtag ac timing waveform recommended operating supply voltages power-up sequence this section describes the sequence in which various voltages must be applied to the part duri ng power-up to ensure proper func tionality. for the pes24t6, the power-up sequence must be as follows: 1. v dd i/o ? 3.3v 2. v dd core, v dd pe, v dd ape ? 1.0v 3. v tt pe ? 1.5v when powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure inter nal latch-up issues are avoided. there are no maximum time limitations in ramping to valid power le vels. the power-down sequence must be in the rev erse order of the power-up sequence. symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for se rdes lvpecl/cml 3.0 3.3 3.6 v v dd pe pci express digita l power 0.9 1.0 1.1 v v dd ape pci express analog power 0.9 1.0 1.1 v v tt pe pci express serial data transmit termination voltage 1.425 1.5 1.575 v v ss common ground 0 0 0 v table 13 pes24t6 operating voltages tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
15 of 33 april 23, 2008 idt 89hpes24t6 data sheet recommended operating temperature power consumption typical power is measured under the following conditions: 25c am bient, 35% total link usage on all ports, typical voltages def ined in table 13 (and also listed below). maximum power is measured under the follow ing conditions: 70c ambient, 85% total li nk usage on all ports, maximum voltages def ined in table 13 (and also listed below). thermal considerations this section describes thermal c onsiderations for the pes24t6 (27mm 2 bxg420 package). the data in table 16 below contains information that is relevant to the thermal performance of the pes24t6 switch. note: the parameter ja(eff) is not the absolute thermal resistance for the package as defi ned by jedec (jesd-51). because resistance can vary with the number of board laye rs, size of the board, and airflow, ja(eff) is the effective thermal resistance. the values for effective ja given above are based on a 10-layer, standard height, full length (4.3?x12.2?) pcie add-in card. grade temperature commercial 0 c to +70 c ambient table 14 pes24t6 operating temperatures number of active lanes per port core supply pcie digital supply pcie analog supply pcie termin- ation supply i/o supply total typ 1.0v max 1.1v typ 1.0v max 1.1v typ 1.0v max 1.1v typ 1.5v max 1.575v typ 3.3v max 3.6v typ power max power 8/4/4/4/4 ma 797 925 1140 1209 430 444 569 603 1 1 3.2w 3.8w watts 0.8 1.02 1.14 1.33 0.43 0.49 0.85 0.95 0.003 0.004 8/4/4/4 ma 705 877 889 1021 363 387 432 490 1 1 2.6w 3.3w watts 0.71 0.97 0.89 1.12 0.36 0.43 0.65 0.77 0.003 0.003 table 15 pes24t6 power consumption symbol parameter value units conditions t j(max) junction temperature 125 o cmaximum t a(max) ambient temperature 70 o c maximum for commercial-rated products ja(effective) effective thermal resistance, junction-to-ambient 10.6 o c/w zero air flow 8.5 o c/w 1 m/s air flow 7.6 o c/w 2 m/s air flow jb thermal resistance, junction-to-board 6.8 o c/w jc thermal resistance, junction-to-case 0.7 o c/w p power dissipation of the device 3.8 watts maximum table 16 thermal specifications for pes24t6, 27x27 mm bxg420 package
16 of 33 april 23, 2008 idt 89hpes24t6 data sheet heat sink table 17 lists heat sink requirements for t he pes24t6 under three common usage scenarios. as shown in this table, a heat sink i s not required in most cases. . thermal usage examples the junction-to-ambient thermal resistance is a measure of a device?s ability to di ssipate heat from the die to its surrounding s in the absence of a heat sink. the general formula to determine ja is: ja = (t j - t a )/p thermal reliability of a dev ice is generally assured when the actual value of t j in the specific system environment being considered is less than the maximum t j specified for the device. usi ng an ambient temperature of 70 o c and assuming a system with 1m/s airflow, the actual value of t j is: t j(actual) = t a + p * ja(eff) = 70 o c + 3.8w * 8.5w/ o c = 102 o c the actual t j of 102 o c is well below the maximum t j of 125 o c specified for the device (shown in tabl e 16). therefore, no heat sink is needed in this scenario. the formula is also useful from a system design perspective. it can be used to determine if a heat sink should b e added to the device based on some desired value of t j . for example, if for reliability purposes the desired t j is 100 o c, then the maximum allowable t a is: t a(allowed) = t j(desired) - (p * ja(effective) ) t a(allowed) = 100 o c - (3.8w * 8.5w/ o c) = 100 o c - 32 o c = 68 o c an appropriate level of increased air flow and/or a heat sink c an be added to achieve this lower ambient temperature. please co ntact ssdhelp@idt.com for further assistance. air flow board size board layers heat sink requirement zero 3.9?x6.2? (expressmodule form factor) or larger 10 or more no heat sink required zero any 14 or more no heat sink required 1 m/s or more any any no heat sink required table 17 heat sink requirements based on air flow and board characteristics
17 of 33 april 23, 2008 idt 89hpes24t6 data sheet dc electrical characteristics values based on systems running at recommended su pply voltages, as shown in table 13. note: see table 8, pin characteristic s, for a complete i/o listing. i/o type parameter description min 1 typ 1 max 1 unit conditions serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 mv v tx-de-ratio de-emphasized differential output voltage -3 -4 db v tx-dc-cm dc common mode voltage -0.1 1 3.7 v v tx-cm-acp rms ac peak common mode output volt- age 20 mv v tx-cm-dc- active-idle-delta abs delta of dc common mode voltage between l0 and idle 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 mv v tx-idle-diffp electrical idle diff peak output 20 mv v tx-rcv-detect voltage change during receiver detection 600 mv rl tx-diff transmitter differential return loss 12 db rl tx-cm transmitter common mode return loss 6 db z tx-deff-dc dc differential tx impedance 80 100 120 z ose single ended tx impedance 40 50 60 transmitter eye diagram tx eye height (de-emphasized bits) 505 650 mv transmitter eye diagram tx eye height (transition bits) 800 950 mv pcie receive v rx-diffp-p differential input voltage (peak-to-peak) 175 1200 mv v rx-cm-ac receiver common-mode voltage for ac coupling 150 mv rl rx-diff receiver differential return loss 15 db rl rx-cm receiver common mode return loss 6 db z rx-diff-dc differential input impedance (dc) 80 100 120 z rx-comm-dc single-ended input impedance 40 50 60 z rx-comm-high- z-dc powered down input common mode impedance (dc) 200k 350k v rx-idle-det- diffp-p electrical idle detect threshold 65 175 mv pcie refclk c in input capacitance 1.5 ? pf table 18 dc electrical characteristics (part 1 of 2)
18 of 33 april 23, 2008 idt 89hpes24t6 data sheet other i/os low drive output i ol ?2.5?ma v ol = 0.4v i oh ?-5.5?ma v oh = 1.5v high drive output i ol ?12.0?ma v ol = 0.4v i oh ?-20.0?ma v oh = 1.5v schmitt trig- ger input (sti) v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd io + 0.5 v? input v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd io + 0.5 v? capacitance c in ??8.5pf ? leakage inputs ? ? + 10 av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 av dd i/o (max) 1. minimum, typical, and maximum values meet the requirements under pci specification 1.1. i/o type parameter description min 1 typ 1 max 1 unit conditions table 18 dc electrical characteristics (part 2 of 2)
19 of 33 april 23, 2008 idt 89hpes24t6 data sheet package pinout ? 420-bga si gnal pinout for pes24t6 the following table lists the pin number s and signal names for the pes24t6 device. pin function alt pin function alt pin function alt pin function alt a1 v ss b9 msmbdat c17 v dd io d25 v ss a2 v ss b10 ssmbaddr_2 c18 v ss d26 perefclkn2 a3 v dd io b11 ssmbaddr_5 c19 v dd io e1 v ss a4 jtag_tdi b12 ssmbdat c20 v ss e2 v ss a5 jtag_tms b13 v ss c21 v dd io e3 v ss a6 msmbaddr_1 b14 swmode_0 c22 gpio_10 1 e4 v ss a7 msmbaddr_3 b15 swmode_2 c23 v dd io e5 p01mergen a8 msmbclk b16 v ss c24 v ss e6 v dd core a9 ssmbaddr_1 b17 v dd io c25 v ss e7 v dd core a10 ssmbaddr_3 b18 gpio_00 1 c26 perefclkp2 e8 v ss a11 ssmbclk b19 gpio_02 1 d1 perefclkp1 e9 v dd core a12 cclkus b20 gpio_04 1 d2 v ss e10 v ss a13 cclkds b21 gpio_06 d3 v ss e11 v dd core a14 v ss b22 msmbsmode d4 p45mergen e12 v ss a15 swmode_1 b23 refclkm d5 v dd core e13 v dd core a16 swmode_3 b24 v dd io d6 v dd core e14 v ss a17 perstn b25 v ss d7 v ss e15 v dd core a18 rsthalt b26 v ss d8 v dd core e16 v ss a19 gpio_01 1 c1 perefclkn1 d9 v ss e17 v dd core a20 gpio_03 1 c2 v ss d10 v dd core e18 v ss a21 gpio_05 1 c3 p23mergen d11 v ss e19 v dd core a22 gpio_07 1 c4 v dd core d12 v dd core e20 v dd core a23 v ss c5 v dd io d13 v dd core e21 v dd core a24 gpio_09 1 c6 v ss d14 v ss e22 v ss a25 v ss c7 v dd io d15 v dd core e23 v ss a26 v ss c8 v ss d16 v ss e24 v ss b1 v ss c9 v dd io d17 v dd core e25 v ss b2 v ss c10 v ss d18 v dd core e26 v ss b3 v dd io c11 v dd io d19 v dd core f1 v dd core b4 jtag_tck c12 v ss d20 v ss f2 v dd core b5 jtag-tdo c13 v dd io d21 v dd core f3 v dd ape b6 jtag-trst_n c14 v dd core d22 v dd core f4 v ss b7 msmbaddr_2 c15 v dd io d23 gpio_08 1 f5 v ss b8 msmbaddr_4 c16 v dd core d24 v ss f22 v ss table 19 pes24t6 420-pin signal pin-out (part 1 of 3)
20 of 33 april 23, 2008 idt 89hpes24t6 data sheet f23 v ss k4 v dd ape p1 v dd core u24 v dd pe f24 v dd ape k5 v dd ape p2 v ss u25 pe5tp01 f25 v dd core k22 v dd ape p3 v tt pe u26 pe5tn01 f26 v dd core k23 v dd ape p4 v tt pe v1 v dd core g1 pe3tn03 k24 v dd ape p5 v ss v2 v ss g2 pe3tp03 k25 v ss p22 v ss v3 v dd ape g3 v dd pe k26 v ss p23 v tt pe v4 v dd ape g4 pe3rn03 l1 pe3tn01 p24 v tt pe v5 v dd ape g5 pe3rp03 l2 pe3tp01 p25 v ss v22 v dd ape g22 pe4rp00 l3 v dd pe p26 v dd core v23 v dd ape g23 pe4rn00 l4 pe3rn01 r1 pe2tn03 v24 v dd ape g24 v dd pe l5 pe3rp01 r2 pe2tp03 v25 v ss g25 pe4tp00 l22 pe4rp02 r3 v dd pe v26 v dd core g26 pe4tn00 l23 pe4rn02 r4 pe2rn03 w1 pe2tn01 h1 v ss l24 v dd pe r5 pe2rp03 w2 pe2tp01 h2 v ss l25 pe4tp02 r22 pe5rp00 w3 v dd pe h3 v tt pe l26 pe4tn02 r23 pe5rn00 w4 pe2rn01 h4 v tt pe m1 v dd core r24 v dd pe w5 pe2rp01 h5 v ss m2 v ss r25 pe5tp00 w22 pe5rp02 h22 v ss m3 v tt pe r26 pe5tn00 w23 pe5rn02 h23 v tt pe m4 v tt pe t1 v dd core w24 v dd pe h24 v tt pe m5 v ss t2 v ss w25 pe5tp02 h25 v ss m22 v ss t3 v dd ape w26 pe5tn02 h26 v ss m23 v tt pe t4 v dd ape y1 v ss j1 pe3tn02 m24 v tt pe t5 v ss y2 v ss j2 pe3tp02 m25 v ss t22 v ss y3 v tt pe j3 v dd pe m26 v dd core t23 v dd ape y4 v tt pe j4 pe3rn02 n1 pe3tn00 t24 v dd ape y5 v ss j5 pe3rp02 n2 pe3tp00 t25 v ss y22 v ss j22 pe4rp01 n3 v dd pe t26 v dd core y23 v tt pe j23 pe4rn01 n4 pe3r n00 u1 pe2tn02 y24 v tt pe j24 v dd pe n5 pe3rp00 u2 pe2tp02 y25 v ss j25 pe4tp01 n22 pe4rp03 u3 v dd pe y26 v ss j26 pe4tn01 n23 pe4rn03 u4 pe2rn02 aa1 pe2tn00 k1 v ss n24 v dd pe u5 pe2rp02 aa2 pe2tp00 k2 v ss n25 pe4tp03 u22 pe5rp01 aa3 v dd pe k3 v dd ape n26 pe4tn03 u23 pe5rn01 aa4 pe2rn00 pin function alt pin function alt pin function alt pin function alt table 19 pes24t6 420-pin signal pin-out (part 2 of 3)
21 of 33 april 23, 2008 idt 89hpes24t6 data sheet aa5 pe2rp00 ac3 v dd core ad11 v dd pe ae19 pe0tp01 aa22 pe5rp03 ac4 v dd core ad12 v tt pe ae20 v ss aa23 pe5rn03 ac5 v dd core ad13 v dd pe ae21 pe0tp00 aa24 v dd pe ac6 v tt pe ad14 v tt pe ae22 v ss aa25 pe5tp03 ac7 pe1rn03 ad15 v dd pe ae23 v dd core aa26 pe5tn03 ac8 v dd ape ad16 v dd ape ae24 v dd core ab1 v ss ac9 pe1rn02 ad17 v ss ae25 v ss ab2 v ss ac10 v dd ape ad18 v dd pe ae26 v ss ab3 v dd core ac11 pe1rn01 ad19 v dd pe af1 v ss ab4 v dd core ac12 v tt pe ad20 v tt pe af2 v ss ab5 v dd core ac13 pe1rn00 ad21 v dd pe af3 v dd core ab6 v ss ac14 v tt pe ad22 v ss af4 v dd core ab7 pe1rp03 ac15 pe0rn03 ad23 v dd core af5 v dd core ab8 v ss ac16 v dd ape ad24 v dd core af6 v ss ab9 pe1rp02 ac17 pe0rn02 ad25 v ss af7 pe1tn03 ab10 v dd ape ac18 v dd ape ad26 v ss af8 v ss ab11 pe1rp01 ac19 pe0rn01 ae1 v ss af9 pe1tn02 ab12 v ss ac20 v tt pe ae2 v ss af10 v dd core ab13 pe1rp00 ac21 pe0rn00 ae3 v dd core af11 pe1tn01 ab14 v dd ape ac22 v ss ae4 v dd core af12 v dd core ab15 pe0rp03 ac23 v dd core ae5 v ss af13 pe1tn00 ab16 v ss ac24 v dd core ae6 v ss af14 v dd core ab17 pe0rp02 ac25 v ss ae7 pe1tp03 af15 pe0tn03 ab18 v dd ape ac26 v ss ae8 v ss af16 v dd core ab19 pe0rp01 ad1 v ss ae9 pe1tp02 af17 pe0tn02 ab20 v ss ad2 v ss ae10 v ss af18 v ss ab21 pe0rp00 ad3 v dd core ae11 pe1tp01 af19 pe0tn01 ab22 v ss ad4 v dd core ae12 v ss af20 v ss ab23 v dd core ad5 v dd core ae13 pe1tp00 af21 pe0tn00 ab24 v dd core ad6 v tt pe ae14 v ss af22 v ss ab25 v ss ad7 v ss ae15 pe0tp03 af23 v dd core ab26 v ss ad8 v dd pe ae16 v ss af24 v dd core ac1 v ss ad9 v ss ae17 pe0tp02 af25 v ss ac2 v ss ad10 v dd pe ae18 v ss af26 v ss pin function alt pin function alt pin function alt pin function alt table 19 pes24t6 420-pin signal pin-out (part 3 of 3)
22 of 33 april 23, 2008 idt 89hpes24t6 data sheet power pins v dd core v dd core v dd core v dd io v dd pe v dd ape v tt pe c4 f2 ae3 a3 g3 f3 h3 c14 f25 ae4 b3 g24 f24 h4 c16 f26 ae23 b17 j3 k3 h23 d5 m1 ae24 b24 j24 k4 h24 d6 m26 af3 c5 l3 k5 m3 d8 p1 af4 c7 l24 k22 m4 d10 p26 af5 c9 n3 k23 m23 d12 t1 af10 c11 n24 k24 m24 d13 t26 af12 c13 r3 t3 p3 d15 v1 af14 c15 r24 t4 p4 d17 v26 af16 c17 u3 t23 p23 d18 ab3 af23 c19 u24 t24 p24 d19 ab4 af24 c21 w3 v3 y3 d21 ab5 c23 w24 v4 y4 d22 ab23 aa3 v5 y23 e6 ab24 aa24 v22 y24 e7 ac3 ad8 v23 ac6 e9 ac4 ad10 v24 ac12 e11 ac5 ad11 ab10 ac14 e13 ac23 ad13 ab14 ac20 e15 ac24 ad15 ab18 ad6 e17 ad3 ad18 ac8 ad12 e19 ad4 ad19 ac10 ad14 e20 ad5 ad21 ac16 ad20 e21 ad23 ac18 f1 ad24 ad16 table 20 pes24t6 power pins
23 of 33 april 23, 2008 idt 89hpes24t6 data sheet ground pins v ss v ss v ss v ss v ss a1 d14 h5 y25 ae2 a2 d16 h22 y26 ae5 a14 d20 h25 ab1 ae6 a23 d24 h26 ab2 ae8 a25 d25 k1 ab6 ae10 a26 e1 k2 ab8 ae12 b1 e2 k25 ab12 ae14 b2 e3 k26 ab16 ae16 b13 e4 m2 ab20 ae18 b16 e8 m5 ab22 ae20 b25 e10 m22 ab25 ae22 b26 e12 m25 ab26 ae25 c2 e14 p2 ac1 ae26 c6 e16 p5 ac2 af1 c8 e18 p22 ac22 af2 c10 e22 p25 ac25 af6 c12 e23 t2 ac26 af8 c18 e24 t5 ad1 af18 c20 e25 t22 ad2 af20 c24 e26 t25 ad7 af22 c25 f4 v2 ad9 af25 d2 f5 v25 ad17 af26 d3 f22 y1 ad22 ? d7 f23 y2 ad25 ? d9 h1 y5 ad26 ? d11 h2 y22 ae1 ? table 21 pes24t6 ground pins
24 of 33 april 23, 2008 idt 89hpes24t6 data sheet alternate signal functions signals listed alphabetically pin gpio alternate b18 gpio[0] p2rstn a19 gpio[1] p4rstn b19 gpio[2] ioexpintn0 a20 gpio[3] ioexpintn1 b20 gpio[4] ioexpintn2 a21 gpio[5] ioexpintn3 a22 gpio[7] gpen d23 gpio[8] p1rstn a24 gpio[9] p3rstn c22 gpio[10] p5rstn table 22 pes24t6 alternate signal functions signal name i/o type location signal category cclkds i a13 system cclkus i a12 gpio_00 i/o b18 general purpose input/output gpio_01 i/o a19 gpio_02 i/o b19 gpio_03 i/o a20 gpio_04 i/o b20 gpio_05 i/o a21 gpio_06 i/o b21 gpio_07 i/o a22 gpio_08 i/o d23 gpio_09 i/o a24 gpio_10 i/o c22 jtag_tck i b4 jtag jtag_tdi i a4 jtag_tdo o b5 jtag_tms i a5 jtag_trst_n i b6 table 23 89pes24t6 alphabetical signal list (part 1 of 5)
25 of 33 april 23, 2008 idt 89hpes24t6 data sheet msmbaddr_1 i a6 smbus msmbaddr_2 i b7 msmbaddr_3 i a7 msmbaddr_4 i b8 msmbclk i/o a8 msmbdat i/o b9 msmbsmode i b22 system p01mergen i e5 system p23mergen i c3 p45mergen i d4 pe0rn00 i ac21 pci express pe0rn01 i ac19 pe0rn02 i ac17 pe0rn03 i ac15 pe0rp00 i ab21 pe0rp01 i ab19 pe0rp02 i ab17 pe0rp03 i ab15 pe0tn00 o af21 pe0tn01 o af19 pe0tn02 o af17 pe0tn03 o af15 pe0tp00 o ae21 pe0tp01 o ae19 pe0tp02 o ae17 pe0tp03 o ae15 pe1rn00 i ac13 pe1rn01 i ac11 pe1rn02 i ac9 pe1rn03 i ac7 pe1rp00 i ab13 pe1rp01 i ab11 pe1rp02 i ab9 signal name i/o type location signal category table 23 89pes24t6 alphabetical signal list (part 2 of 5)
26 of 33 april 23, 2008 idt 89hpes24t6 data sheet pe1rp03 i ab7 pci express (cont.) pe1tn00 o af13 pe1tn01 o af11 pe1tn02 o af9 pe1tn03 o af7 pe1tp00 o ae13 pe1tp01 o ae11 pe1tp02 o ae9 pe1tp03 o ae7 pe2rn00 i aa4 pe2rn01 i w4 pe2rn02 i u4 pe2rn03 i r4 pe2rp00 i aa5 pe2rp01 i w5 pe2rp02 i u5 pe2rp03 i r5 pe2tn00 o aa1 pe2tn01 o w1 pe2tn02 o u1 pe2tn03 o r1 pe2tp00 o aa2 pe2tp01 o w2 pe2tp02 o u2 pe2tp03 o r2 pe3rn00 i n4 pe3rn01 i l4 pe3rn02 i j4 pe3rn03 i g4 pe3rp00 i n5 pe3rp01 i l5 pe3rp02 i j5 pe3rp03 i g5 pe3tn00 o n1 pe3tn01 o l1 pe3tn02 o j1 signal name i/o type location signal category table 23 89pes24t6 alphabetical signal list (part 3 of 5)
27 of 33 april 23, 2008 idt 89hpes24t6 data sheet pe3tn03 o g1 pci express (cont.) pe3tp00 o n2 pe3tp01 o l2 pe3tp02 o j2 pe3tp03 o g2 pe4rn00 i g23 pe4rn01 i j23 pe4rn02 i l23 pe4rn03 i n23 pe4rp00 i g22 pe4rp01 i j22 pe4rp02 i l22 pe4rp03 i n22 pe4tn00 o g26 pe4tn01 o j26 pe4tn02 o l26 pe4tn03 o n26 pe4tp00 o g25 pe4tp01 o j25 pe4tp02 o l25 pe4tp03 o n25 pe5rn00 i r23 pe5rn01 i u23 pe5rn02 i w23 pe5rn03 i aa23 pe5rp00 i r22 pe5rp01 i u22 pe5rp02 i w22 pe5rp03 i aa22 pe5tn00 o r26 pe5tn01 o u26 pe5tn02 o w26 pe5tn03 o aa26 pe5tp00 o r25 pe5tp01 o u25 pe5tp02 o w25 signal name i/o type location signal category table 23 89pes24t6 alphabetical signal list (part 4 of 5)
28 of 33 april 23, 2008 idt 89hpes24t6 data sheet pe5tp03 o aa25 pci express (cont.) perefclkn1 i c1 perefclkn2 i d26 perefclkp1 i d1 perefclkp2 i c26 perstn i a17 system refclkm i b23 pci express rsthalt i a18 system ssmbaddr_1 i a9 smbus ssmbaddr_2 i b10 ssmbaddr_3 i a10 ssmbaddr_5 i b11 ssmbclk i/o a11 ssmbdat i/o b12 swmode_0 i b14 system swmode_1 i a15 swmode_2 i b15 swmode_3 i a16 v dd core, v dd ape, v dd io, v dd pe , v tt pe see table 20 for a listing of power pins. v ss see table 21 for a listing of ground pins. signal name i/o type location signal category table 23 89pes24t6 alphabetical signal list (part 5 of 5)
29 of 33 april 23, 2008 idt 89hpes24t6 data sheet pes24t6 pinout ? top view 12345678910111213141516 vss (ground) v dd core (power) a b v dd i/o (power) 17 18 19 20 21 22 23 24 25 26 c d e f g h j k l m n p r t u v w y aa ab ac ad ae af v tt pe (power) v dd pe (power) v dd ape (power) signals 12345678910111213141516 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af x x x x x x x x x x xx xx x xx x x x x x xx x
30 of 33 april 23, 2008 idt 89hpes24t6 data sheet pes24t6 package drawing ? 420-pin bx420/bxg420
31 of 33 april 23, 2008 idt 89hpes24t6 data sheet pes24t6 package drawing ? page two
32 of 33 april 23, 2008 idt 89hpes24t6 data sheet revision history february 8, 2007 : initial publication. april 4, 2007 : in table 3, revised description for msmbclk signal. may 30, 2007 : added zg device revision to ordering information. november 14, 2007 : added new parameter, termination resistor , to table 9, input clock requirements. march 25, 2008 : added jb and jc parameters to table 16, thermal specifications. april 23, 2008 : added 1zc device revision to ordering information.
33 of 33 april 23, 2008 idt 89hpes24t6 data sheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ? ordering information valid combinations 89hpes24t6zcbx 420-pin bx420 package, commercial temperature 89hpes24t6zgbx 420-pin bx420 package, commercial temperature 89HPES24T61ZCBX 420-pin bx420 package, commercial temperature 89hpes24t6zcbxg 420-pin green bx420 package, commercial temperature 89hpes24t6zgbxg 420-pin green bx420 package, commercial temperature 89HPES24T61ZCBXg 420-pin green bx420 package, commercial temperature nn a aaa nnan aa a operating voltage device family product package temp range h blank commercial temperature (0c to +70c ambient) product family 89 serial switching product bx420 420-ball bga bx 24t6 24-lane, 6-port 1.0v +/- 0.1v core voltage detail pci express switch pes legend a = alpha character n = numeric character bxg420 420-ball bga, green bxg aaa device revision zc zc revision zg zg revision 1zc 1zc revision

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